Description

This lab course is offered to provide the student with the practical skills to verify an FPGA design in simulation environment. The student will build various components of a test environment beginning with a basic testbench using manual verification and progressing to a more robust self-checking test environment. This includes generating constrained random stimulus and predicting, monitoring, and checking responses. The students will also create a regression test suite and evaluate coverage. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.