Computer Architecture, Network Systems
- Heterogeneous Computing, Software Defined Networking, Machine Learning, High Performance Networking, Parallel and Distributed Processing, Embedded Systems.
- Data analytics with machine learning, acceleration of network data plane, secure sharing of healthcare data, software defined networking, network measurement.
- Ph.D.: Computer Science, (2005), University of California Riverside - Riverside, CA
Dissertation/Thesis Title: Performance Evaluation and Low Power Design of Network Processors
- Other: Computer Science and Engineering, (2000), Huazhong University of Science and Technology - Wuhan, Hubei, China
- Other: Computer Science and Engineering, (1996), Huazhong University of Science and Technology - Wuhan, Hubei, China
Yan Luo earned his Ph.D. in Computer Science from the University of California Riverside in 2005 and his BE and ME degrees from Huazhong University of Science and Technology in 1996 and 2000, respectively. While his research interest spans broadly computer architecture and network systems, Prof. Luo’s current research focuses on machine learning, heterogeneous architecture and systems, software defined networks. He has served on the program committee of numerous international conferences and as a guest editor and referee of premier journals. Prof. Luo directs the Laboratory of Advanced Computing and Networking Systems, which has been supported by National Science Foundation, Intel, Raytheon/BBN, Xilinx and Altera. Prof. Luo has published over 70 peer-reviewed journal and conference papers with two best paper awards. Prof. Luo is a member of IEEE and ACM.
Selected Awards and Honors
- Outstanding Student Award, Huazhong Univ. of Sci. & Tech., China, Scholarship/Research - Huazhong Univ. of Sci. & Tech., China
- Best Paper Award (2010), Scholarship/Research - IEEE
- ECE Teaching Award (2009) - ECE,University of Massachusetts Lowell
- Chancellor's Distinguished Fellowship (2000) - University of California Riverside
- Excellent Employee Award (1997) - Nortel R&D, Guangzhou, China
- Chen, S., Liu, C., Cao, Y., Luo, Y., Chen, G., Vokkarane, V.M., Ma, Y., Hou, P. (2017). A New Deep Learning-based Food Recognition System for Dietary Assessment on An Edge Computing Service Infrastructure. IEEE Transactions on Services Computing, PP(99) 1-1.
- Li, P., Xu, C., Luo, Y., Cao, Y., Mathew, J., Ma, Y. (2017). CareNet: Building a Secure Software-defined Infrastructure for Home-based Healthcare (pp. 69–72). ACM
- Liu, C., Cao, Y., Luo, Y., Chen, G., Vokkarane, V.M., Ma, Y. (2016). DeepFood: Deep Learning-Based Food Image Recognition for Computer-Aided Dietary Assessment (pp. 37–48). Springer-Verlag New York, Inc.
- Wang, H., Tahan, M., Hu, T. (2016). Effects of rest time on equivalent circuit model for a li-ion battery (2016-July: pp. 3101 - 3106). Proceedings of the American Control Conference
- He, L., Miskell, T., Liu, R., Yu, H., Xu, H., Luo, Y. (2016). Scalable 2D K-SVD parallel algorithm for dictionary learning on GPUs (pp. 11 - 18). 2016 ACM International Conference on Computing Frontiers - Proceedings
- Tian, C., Wang, Y., Luo, Y., Jiang, H., Liu, W., Wu, J., Yin, H. (2016). Minimizing Content Reorganization and Tolerating Imperfect Workload Prediction for Cloud-based Video-on-Demand Services. IEEE Transactions on Services Computing, 9(6).
- Wu, X., Li, P., Ran, Y., Luo, Y. (2016). Network Measurement for 100Gbps Links Using Multicore Processors. INDIS’16 Workshop Affiliated with ACM/IEEE SuperComputing (SC)
- Xu, C., Wu, X., Luo, Y., Tierney, B., Bezerra, J. (2016). Pepple: Programmable network measurement for troubleshooting soft failures (pp. 136-141).
- Li, P., Luo, Y. (2016). P4GPU: Acceleration of programmable data plane using a CPU-GPU heterogeneous architecture (pp. 168-175).
- Li, P., Luo, Y., Yang, J. (2015). Run-time Reprogrammable Heterogeneous Architecture for Transparent Acceleration of Dynamic Workloads. Journal of Parallel and Distributed Computing, 86(C) 45-61.
- Li, P., Luo, Y., Zhang, N., Cao, Y. (2015). HeteroSpark: a Heterogeneous CPU/GPU Spark Platform for Machine Learning Algorithms (pp. 347–348).
- Tian, C., Wang, Y., Luo, Y., Jiang, H., Liu, W., Wu, J., Yin, H. (2015). Minimizing Content Reorganization and Tolerating Imperfect Workload Prediction for Cloud-based Video-on-Demand Services (PP:99 pp. 1-1). Services Computing, IEEE Transactions on
- Li, P., Luo, Y. (2015). Mapping a P4 Program onto GPU Target Architecture. 2nd P4 Workshop
- He, L., Luo, Y., Liu, R., Hengyong, Y., Cao, Y., Chen, X., Son, S.W. (2015). Bisection and twisted SVD on GPU (pp. 1-7). IEEE High Performance Extreme Computing Conference (HPEC)
- Yin, H., Qiao, B., Luo, Y., Tian, C., Yang, R. (2015). Demystifying Commercial Content Delivery Networks in China, Concurrency and Computation: Practice and Experience. Wiley
- Li, P., Luo, Y., Cao, Y., Zhang, N. (2015). HeteroSpark: A Heterogeneous CPU/GPU Spark Platform for Deep Learning Algorithms. Spark Summit East
- He, L., Luo, Y., Cao, Y. (2014). Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition (pp. 104–104).
- Liu, R., Luo, Y., Yu, H. (2014). GPU-based acceleration for interior tomography. IEEE Access, 2 757-770.
- Eramo, V., Hesselbach-Serra, X., Luo, Y. (2014). Innovative techniques for power consumption saving in telecommunication networks. Journal of Electrical and Computer Engineering, 2014.
- Li, S., Murray, E., Luo, Y. (2014). Programmable Network Traffic Classification with OpenFlow Extensions (pp. 269-302). CRC Press
- Yin, H., Jiang, Y., Lin, C., Luo, Y., Liu, Y. (2014). Big data: Transforming the design philosophy of future internet. IEEE Network, 28(4) 14-19.
- Li, P., Huang, X., Zhao, T., Luo, Y., Cao, Y. (2014). Sparkling: Identification of Task Skew and Speculative Partition of Data for Spark Applications. Spark Summit
- He, L., Luo, Y., Cao, Y. (2014). Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition. The 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines
- Zhang, Z., Cheng, X., Su, S., Wang, Y., Shuang, K., Luo, Y. (2013). A unified enhanced particle swarm optimization-based virtual network embedding algorithm. International Journal of Communication Systems, 26(8) 1054-1073.
- Luo, Y., Chen, X., Wang, J. (2013). A virtual network embedding algorithm for providing stronger connectivity in the residual networks. Journal of Networks, 8(4) 779-786.
- Luo, Y., Zhang, C., Ficarra, T., Murray, E. (2011). The design, performance evaluation and use cases of a virtualized programmable edge node for network innovations. International Journal of Communication Networks and Distributed Systems, 6(3) 249-267.
- Cheng, X., Su, S., Zhang, Z., Wang, H., Yang, F., Luo, Y., Wang, J. (2011). Virtual network embedding through topology-aware node ranking. ACM SIGCOMM Computer Communication Review, 41(2) 38-47.
- Luo, Y. (2010). Network I/O Virtualization for Cloud Computing. IT professional, 12(5) 36-41.
- Luo, Y., Yu, J., Yang, J., Bhuyan, L.N. (2007). Conserving network processor power consumption by exploiting traffic variability. ACM Transactions on Architecture and Code Optimization (TACO), 4(1).
- Energy-aware Virtual Network Embedding Through Consolidation. - The 1st IEEE INFOCOM Workshop on Communications and Control for Sustainable Energy Systems, March 2012 - Orlando FL.
- Exploration of Memory Hierarchy for Heterogeneous Computing Architecture. - The 3rd Workshop on SoCs, Heterogeneous Architectures and Workloads, February 2012 - New Orleans, LA.
- Virtual Network Embedding with Border Matching. - The 4th IEEE International Conference on Communication Systems and Networks, January 2012 - Bangalore, India.
- Multi-dimensional Resource Integrated Scheduling in a Shared Data Center - The First International Workshop on Data Center Performance, June 2011 - Minneapolis, MN
- Reconfigurable Logic Accelerated Heterogeneous Multicore Architecture for Dynamic Workloads - 2nd Workshop on SoC Architecture, Accelerators and Workloads, in conjunction with IEEE HPCA, February 2011 - San Antonio, TX
- Reconfigurable Logic Accelerated Heterogeneous Multicore Architecture for Dynamic Workloads. - Intel Embedded Research and Education Summit., February 2011 - Chandler, AZ
- Intelligent NIC Based Packet Switching for Scalable Data Center Networking - Intel Embedded Education Summit, 2010 - Chandler, AZ
- UMass Lowell Programmable Edge Node: Architecture, Federation and Usage. - GENI Tutorial, NSF 9th GENI Engineering Conference, November 2010 - Washington DC
- Virtual Switching with Programmable NICs for Scalable Data Center Networking. - ACM SIGCOMM, September 2010 - New Delhi, India.
- Accelerated Virtual Switching with Programmable NICs for Scalable Data Center Networking. - ACM SIGCOMM Virtualized Infrastructure Systems and Architectures (VISA) Workshop, September 2010 - New Delhi, India
- High Performance Flow Feature Extraction with Multicore Processors, IEEE International Conference on Network, Architecture and Storage. - IEEE International Conference on Network, Architecture and Storage, July 2010 - Macau, China
- Science and Engineering Issues of Network Virtualization, July 2010 - Shanghai Jiaotong University, China
- Science and Engineering Issues of Network Virtualization. - Invited Talk, ECE Department, Beijing University of Posts and Telecommunications, June 2010 - Beijing,China
- Science and Engineering Issues of Network Virtualization. - Invited Talk, ECE Department, University of Massachusetts, Amherst, April 2010 - University of Massachusetts, Amherst
- Accelerating OpenFlow Switching with Network Processors, ACM Symposium on Architectures for Networking and Communications Systems. - ACM Symposium on Architectures for Networking and Communications Systems, October 2009 - Princeton, NJ
- A DFA-Based Regular Expression Matching Engine on a NetFPGA Platform, NetFPGA Developers Workshop - NetFPGA Developers Workshop, August 2009 - Stanford University, Palo Alto, CA
- Discernibility Analysis and Accuracy Improvement of Machine Learning Algorithms for Network Intrusion Detection. - IEEE International Conference on Communications, June 2009 - Dresden, Germany
- Distributed Intrusion Detection with Intelligent Network Interfaces for Future Networks - IEEE International Conference on Communications, June 2009 - Dresden, Germany
- A Performance Study of Network I/O Accelerators for Network Virtualization, - Workshop on The Influence of I/O on Microprocessor Architecture, February 2009 - Raleigh, NC, February 15, 2009
- Trace Capture and Analysis on GENI for Security Research., January 2009 - California Davis
- Acceleration of Decision Tree Searching for IP Traffic Classification, ACM Symposium on Architectures for Networking and Communications Systems - ACM Symposium on Architectures for Networking and Communications Systems, November 2008 - San Jose, CA, Nov
- Programmable Architecture for Future High Performance Network, November 2008 - University of Massachusetts Boston
- Programmable Edge Node for GENI - 3rd GENI Engineering Conference, October 2008 - Palo Alto, CA
- The Design of A Programmable Network Edge Node with Hybrid Multi-core Processors for Virtual Networks - IEEE International Conference on Computer Communications and Networks, August 2008 - St. Thomas, VI
- Design of High Performance Pattern Matching Engine Through Compact Deterministic Finite Automata - IEEE/ACM Design Automation Conference (DAC), June 2008 - Anaheim, CA
- Fault Tolerant Practices on Network Processors for Dependable Network Processing - 13th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems, in conjunction with IPDPS'08, April 2008 - Miami, FL
- Modeling and Analysis of Power in Multicore Network Processors - Fourth IEEE Workshop on High-Performance, Power-Aware Computing, in conjunction with IPDPS'08, April 2008 - Miami, Fl
- High Performance Network Processing with Programmable Architectures, April 2008 - Kingston, RI
- Performance Evaluation of Regular Expression Matching using Intel IXP Network Processors - Intel Embedded and Communication Summit, February 2008
- A High Speed Deep Packet Inspection Engine using Compact Finite Automata - ACM Symposium on Architectures for Networking and Communications Systems, December 2007 - Orlando, FL
- High Performance Regular Expression Matching with Network Processors, September 2007
- Acceleration of Network Processing Using Programmable Architectures, June 2007 - Boxborough, MA
- Compact State Machines for High Performance Pattern Matching - IEEE/ACM Design Automation Conference (DAC), June 2007 - San Diego, CA
- RemCo: A High Speed Regular Expression Matching Engine Using Compact Finite Automata, March 2007 - Hudson, MA
- Efficient Memory Utilization on Network Processors for Deep Packet Inspection, January 2007 - Chelmsford, MA
- Efficient Memory Utilization on Network Processors for Deep Packet Inspection - ACM Symposium on Architecture for Networking and Communications Systems, December 2006 - San Jose, CA
- Network Processors: Architecture and Applications, December 2005 - UMass Lowell
- Optimal Network Processor Topologies for Efficient Packet Processing - IEEE Globecom 2005, 2005 - St Louis, MO
- A TCP Splicer using Network Processors - ACM Symposium on Architecture for Networking and Communications Systems, October 2005 - Princeton, NJ
- SpliceNP: A TCP Splicer using an Network Processor, October 2005 - Princeton, NJ
- Protocol Offloading using an IXP2400 Network Processor - Intel IXA 2005 Summit, September 2005 - Hudson, MA
- Network Processors: Architecture, Performance Evaluation and Applications., September 2005 - UMass Lowell
- Implementation and Design of A Content-aware Switch Using A Network Processor - IEEE Symposium on High Performance Interconnects, August 2005 - Palo Alto, CA
- Low Power Network Processor Design Using Clock Gating - IEEE/ACM Design Automation Conference (DAC), June 2005 - Ahaheim, California
- Utilizing Formal Assertions for System Design of Network Processors - Design Forum, Design Automation and Test in Europe (DATE), 2004., 2004
- Evaluating the Impact of Architectural Features on Communication Benchmarks, Communications in Computing. - Communications in Computing, June 2002 - Nevada, USA
- Experiences with Oasis+: A Fault Tolerant Storage System - IEEE International Conference on Cluster Computing, October 2001 - Newport Beach, CA,
- The Oasis+ Dependable Distributed Storage System - Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing., December 2000 - Los Angeles, CA
Selected Intellectual Property
- Patent - Xuejun, L."A Long-wave InAs/GaAs Quantum Dot Infrared Photodetector Based on Two-photon Absorption Process with Ultra-low Noise Level,"
- Liu, J., Wang, Z., Huang, Y., Lu, X."Staged amplifier for lower noise figure and higher saturation power,î United States Patent Application," 20040085622 United States
Selected Contracts, Fellowships, Grants and Sponsored Research
- Curriculum Development on Offload Architecture and Middleware (2013), -
Luo, Y. (Principal)
- From Profiling to Simulation: A Simics-Based Pedagogical Approach for Teaching H (2012), -
Luo, Y. (Principal)
- New Embedded Computing Curriculum with Intel Atom Based Architectures at UMass Lo (2011), -
Luo, Y. (Principal)
- REU Funding - Design and Performance Evaluation of a Programmable Edge Node with (2009), Contract - NATIONAL SCIENCE FOUNDATION
Luo, Y. (Principal)
- Design and Performance Evaluation of a Programmable Edge Node with x86 Multi-core (2008), Contract - NATIONAL SCIENCE FOUNDATION
Luo, Y. (Principal)
- Performance Evaluation and Acceleration of an Open Source VPN System on Tolapai P (2008), Grant -
Luo, Y. (Principal)
- Travel Grant Support for IEEE ICCCN 2010 Conference (2009), Grant -
Luo, Y. (Principal)
- Programmable Network Infrastructure with Emerging Technologies (2007), Grant - National Science Foundation
Chen, G. (Co-Principal), Luo, Y. (Principal), Chandra, K., Wang, J.
- Design and Performance Evaluation of High Speed Deep Packet Inspection Systems (2007), Grant -
Luo, Y. (Principal)
- Programmable Network Infrastructure with Emerging Technologies (2007), - National Science Foundation
Chandra, K. (Co-Principal), Luo, Y. (Principal)