03/31/2026
By Tarush Tiwari

The Kennedy College of Sciences, Department of Physics and Applied Physics, invites you to attend a Master’s thesis, doctoral dissertation defense by Tarush Tiwari on “High-fidelity parametric operations in multi-qubit circuit QED architectures.”

Candidate Name: Tarush Tiwari
Degree: Master’s
Defense Date: Tuesday, April 7, 2026
Time: 11 a.m. to 1 p.m.
Location: 136 Olney Hall, North Campus
Thesis/Dissertation Title: High-fidelity parametric operations in multi-qubit circuit QED architectures

Committee:

  • Advisor: Nishant Agarwal, Ph.D., Department of Physics and applied Physics, University of Massachusetts Lowell
  • Archana Kamal, Ph.D., Department of Physics and Astronomy, Northwestern University
  • Leonardo Ranzani, Ph.D., Quantum, Photonics and Computing group, RTX BBN Technologies
  • Hugo Ribeiro, Ph.D., Department of Physics and applied Physics, University of Massachusetts Lowell

Brief Abstract:

Tunable couplers constitute a critical modality for implementing fast and on-demand interactions in multi-mode superconducting circuits. These couplers typically include a flux-tunable circuit geometry which can implement a strong frequency-selective interaction between desired modes by modulating the bias flux at a linear combination (sum or difference) of mode frequencies. One such design is the recently proposed dual-transmon coupler (DTC), which facilitates strong exchange interaction between the data qubits while minimizing ZZ coupling simultaneously. This makes the DTC especially useful for realizing high-fidelity two-qubit gate operations such as iSWAP or CZ.

In this thesis, I will discuss the implementation and experimental characterization of the two-qubit iSWAP gate on a two-transmon system incorporating a DTC. First, I will present a brief discussion of the device design and some salient characteristics of DTC, including a discussion of ZZ cancellation and demonstration of fast parametric interactions. I will then discuss the robust phase estimation routine used for calibration and pulse optimization of the iSWAP gate. Finally, I will present the process tomography and two-qubit randomized benchmarking results confirming the realization of a 40-ns iSWAP gate with 99.7% fidelity.