07/22/2025
By Danielle Fretwell

The Francis College of Engineering, Department of Electrical and Computer Engineering, invites you to attend a Master's Thesis defense by Sriram Krishnamoorthy on: "Investigating Side-Channel Attacks on FPGAs through Correlation Power Analyses."

Candidate Name: Sriram Krishnamoorthy
Degree: Master’s
Defense Date: Friday, August 1, 2025
Time: 11:30 a.m. - 12:30 p.m.
Location: Perry Hall 215

Committee:

  • Advisor: Orlando Arias, Assistant Professor, Electrical and Computer Engineering, University of Massachusetts Lowell
  • Kavitha Chandra, Ph.D., Electrical and Computer Engineering Department, University of Massachusetts Lowell
  • Jean-Francois Millithaler, Ph.D., Electrical and Computer Engineering Department, University of Massachusetts Lowell

Abstract:
As the cost of infrastructure increases, Hardware as a Service (HaaS) vendors have built infrastructure wherein a single machine is shared by multiple tenants. This is normally performed through virtualization techniques. However, this type of sharing has been proven to result in information being leaked through unintended side channels [1, 2, 3]. These side channels occur due to the lack of partitioning between some resources of the computing infrastructure, such as last-level caches on a CPU package. These side channels can be utilized to reveal information such as private keys, credit card numbers, or any other sensitive data.

Following this trend, FPGAs have been added to HaaS infrastructure by vendors such as Amazon, wherein their F1 instances allow for users to load bitstreams, or FPGA configuration files, into a leased machine configuring the FPGA to the customer's needs. Because FPGAs are not used to their full capacity, vendors have thought about partitioning FPGAs, allowing for multi-tenancy on the FPGA chip themselves. Here, the FPGA is partitioned in logical blocks, and each logical block is assigned to individual tenants. It would appear at first that no resource sharing takes place, as dedicated hardware resources are assigned to each tenant. However, this is not the case: the power distribution network (PDN) in the FPGA is shared across partitions, resulting for potential side channels to occur.

This research simulates PDN-based side-channel attacks on FPGAs by attaching a measuring circuit to a non-ideal PDN which is made to fluctuate by a separate load. Circuits such as finite state machines, random number generators, and a cryptographic core are probed during operation in simulation by these measurement circuits. Through simulation we capture power variations in the PDN through our primitives and study their effect by correlating the fluctuations in measurements seen to the operation of the test circuits. Simulation results demonstrate how the switching frequency and high-power consumption of certain circuit operations increases their vulnerability to attacks. The presented work provides the basis to understanding PDN-based side-channels from a physical level and can serve as the basis for modeling more complex circuits as well as testing possible solutions.