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EECE.5620 VHDL/Verilog Synthesis & Design (Formerly 16.562)

Id: 003302 Credits Min: 3 Credits Max: 3


This course covers digital chip design, synthesis, verification, and test using Hardware Description Languages (HDLs). This class will thoroughly cover important features of the following Hardware Description Languages (HDLs): Verilog, VHDL (VHSIC Hardware Description Language) and System Verilog. These HDLs will be presented with primary emphasis on the synthesizable design aspects of the languages. Therefore, these HDLs will be used for chip design. In addition to using HDLs for digital design, these HDLs will also be used for design verification. Hardware Description Languages (HDLs) will be utilized to design, synthesize and verify digital chip designs. The design and structure of HDL code for effective FPGA and ASIC synthesis will be explored. The design process and verification process for FPGAs and ASICs will be thoroughly reviewed. The Synthesis process for FPGAs and ASICs will thoroughly reviewed, including the following: step by step synthesis process flows, the impact of synthesis constraints, and synthesis scripts for FPGA and ASIC design. Key concepts in functional design verification for ASICs & FPGAs will be explored. Other topics may include the following: High speed digital design, interface to SDRAM devices, embedded processors (hardware, software, test implications), HDL design techniques for effective logic synthesis, chip partitioning, ASIC and FPGA top-down design structure, pipelining, resource/speed trade offs, high speed DSP structures, high speed cache design, resources sharing and design of arbiters. Additional topics to be covered include the following: Design for Test (DFT), Memory Built in Self Test, Logic Built in Self Test, scan chain design, shadow scan design, JTAG, observability bus design, test vector generation & fault coverage.


Pre-Reqs: EECE 2650 Intro Logic Design and EECE 3650 Electronics I.

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