EECE.5625L VHDL/Verilog Synthesis & Design Lab

Description

This lab course is offered to provide the student practical applications of advanced FPGA topics. The lab will focus on advanced language constructs and effective coding for synthesis. Timing closure techniques and synthesis optimization for speed vs power will be explored. Features of synthesis tools including partial reconfiguration, tool reports and clock domain crossing will be evaluated. This course will consist of seven 2-hour labs, each requiring either completion of a worksheet or a detailed report of the results.

Course prerequisites/corequisites are determined by the faculty and approved by the curriculum committees. Students are required to fulfill these requirements prior to enrollment. For courses offered through online or GPS delivery, students are responsible for confirming with the instructor or department that all enrollment requirements have been satisfied before registering.