EECE.4690 VLSI Design (Formerly 16.469/502 & EECE.4690/5020)

Id: 001268 Credits: 3-3

Description

Introduction to CMOS circuits including transmission gate, inverter, NAND, NOR gates, MUXEs, latches and registers. MOS transistor theory including threshold voltage and design equations. CMOS inverter's DC and AC characteristics along with noise margins. Circuit characterization and performance estimation including resistance, capacitance, routing capacitance, multiple conductor capacitance, distributed RC capacitance, multiple conductor capacitance, distributed RC capacitance, switching characteristics incorporating analytic delay models, transistor sizing and power dissipation. CMOS circuit and logic design including fan-in, fan-out, gate delays, logic gate layout incorporating standard cell design, gate array layout, and single as well as two-phase clocking. CMOS test methodologies including stuck-at-0, stuck-at-1, fault models, fault coverage, ATPG, fault grading and simulation including scan-based and self test techniques with signature analysis. A project of modest complexity would be designed to be fabricated at MOSIS.

Prerequisites

EECE.3120 Electronics II Lab and EECE.3660 Electronics II

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