01/04/2023
By Martin Margala

The Francis College of Engineering, Department of Electrical & Computer Engineering, invites you to attend a doctoral proposal defense by Shachivaman Khakilkar on “Open-source CAD tooling for FPGAs."

Candidate Name: Shachivaman Khakilkar
Degree: Doctoral
Defense Date: Jan. 20, 2023
Time: 9 to 11 a.m.
Location: ECE Department Conference Room. Those interested in attending should contact the student shachivaman_khadilkar@student.uml.edu and committee advisor martin_margala@uml.edu.

Advisor: Martin Margala, Department of Electrical & Computer Engineering, University of Massachusetts, Lowell    

Committee Members:

  • Yan Luo, Department of Electrical & Computer Engineering, University of Massachusetts Lowell
  • Vinod Vokkarane, Department of Electrical & Computer Engineering, University of Massachusetts Lowell
  • Ahmed Sanaullah, RedHat

Brief Abstract:
Field Programmable Gate Arrays (FPGAs) have gained popularity in recent years owing to their reprogrammability, power efficiency, and parallel computing capabilities. CAD tooling is needed to map FPGA code to the FPGA hardware. Developing FPGA CAD tools is often challenging. Vendor CAD tools generate good solutions but are closed-source and do not allow developers to customize the tool flow to suit their applications. Vendor CAD tools also have expensive licensing and do not reveal details of the hardware generation process. The issues with vendor tools have made open-source CAD tools for FPGAs a favorable alternative. Open-source tools are free and allow customization. Initially, these tools were built for theoretical FPGA architectures, but more recently, architectural details of a few commercial FPGAs have become available, thus enabling researchers to build open-source tools for commercial devices. However, a performance gap still exists between vendor and academic CAD tools for FPGA hardware generation. The goal of our research is to reduce this gap. We quantify the performance gap between a state-of-the-art vendor CAD tool and a corresponding open-source tool. We present our framework that identifies the mapping between critical policies and input hardware patterns for a given CAD algorithm. We use this mapping to tune the open-source tool for the generation of better hardware quality and present our results from the policy tuning in this work.