Skip to Main Content

Martin Margala


Martin Margala is the Chair, Professor, Deputy Director - AETC in the Francis College of Engineering's Electrical & Computer Engineering Dept. at UMass Lowell.
Martin MargalaChair, Professor, Deputy Director - AETC, UMOVE Co-Director
  • College
    Francis College of Engineering
  • Department
    Electrical & Computer Eng
  • Phone
    (978) 934-2986
  • Email
    martin_margala@uml.edu

Research Interests

Digital & Mixed-Signal VLSI Design & VLSI Testing

Low-Power Memories, Adaptable Circuits and Architectures, SIMD and MIMD Processing, Analog-to-Digital Converter Design, Design for Reliability, Ballistic Operation

Education

  • Ph D: Electrical and Computer Engineering, (1998), University of Alberta, Edmonton, Canada - Edmonton, Canada
  • MS: Electrical Engineering (specialization Microelectronics), (1990), Slovak Technical University, Bratislava, Slovakia. - Bratislava, Slovakia, Europe
    Dissertation/Thesis Title: (specialization Microelectronics)

Selected Awards and Honors

  • Appreciation Certificate - IEEE NATW Workshop.
  • Fulbright-Czech Technical University Distinguished Chair in El. Engineering (2015) - Fulbright
  • Best Paper Awards (2012) - IEEE North Atlantic Test Workshop, Woburn, MA, May 9-11, 2012.
  • Order Of An Engineer (2007) - Order Of An Engineer
  • Best Paper Award (2006) - NASA/ESA
  • Best Paper Award (2003) - IEEE North Atlantic Test Workshop
  • DAAD Fellowship (2001) - DAAD Fellowship (Awarded by the German Academic Exchange Service)
  • Honourable Member (2000) - Cambridge Who's Who _ Honourable Member.

Selected Publications

  • Nguyen, H., Ozmen, C., Dirican, A., Tan, N., Margala, M. (2016). A CMOS Ripple Detector for Voltage Regulator Testing. Journal of Electronic Testing: Theory and Applications (JETTA), 32(2) 227 - 233.
  • Marthi, P., Hossain, N., Millithaler, J., Margala, M. (2016). A new level sensitive D Latch using Ballistic nanodevices (2016-July: pp. 1882 - 1885). Proceedings - IEEE International Symposium on Circuits and Systems
  • Millithaler, J., Marthi, P., Hossain, N., Iniguez-De-La-Torre, I., Mateos, J., Gonzalez, T., Margala, M. (2016). Ballistic deflection transistor very high frequency modeling (2016-August:). Device Research Conference - Conference Digest, DRC
  • Marthi, P., Hossain, N., Wang, H., Millithaler, J., Margala, M., Iniguez-De-La-Torre, I., Mateos, J., Gonzalez, T. (2016). Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(12) 2236 - 2244.
  • Marthi, P., Hossain, N., Wang, H., Millithaler, J., Margala, M., Iniguez-de-la-Torre, I., Mateos, J., Gonzalez, T. (2016). Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 63(12) 2236.
  • Segal, O., Margala, M. (2016). Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud (pp. 132 - 139). 2016 International Conference on High Performance Computing and Simulation, HPCS 2016
  • Qian, Z., Margala, M. (2016). Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(9) 3008 - 3012.
  • Marthi, P., Reza, S.R., Hossain, N., Millithaler, J., Margala, M., Iniguez-de-la-Torre, I., Mateos, J., Gonzalez, T. (2016). Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits (18-20-May-2016: pp. 393 - 396). Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
  • Millithaler, J., Marthi, P., Hossain, N., Margala, M., Iñiguez-de-la-Torre, I., Mateos, J., González, T. (2016). Monte Carlo modeling of ultra-fast operating Ballistic Deflection Transistor (pp. 38-41).
  • Ozmen, C., Dirican, A., Tan, N., Nguyen, H., Margala, M. (2015). A CMOS ripple detector for integrated voltage regulator testing (pp. 1-4).
  • Ozmen, C., Dirican, A., Tan, N., Nguyen, H., Margala, M. (2015). A CMOS ripple detector for integrated voltage regulator testing (pp. 147-150).
  • Segal, O., Colangelo, P., Nasiri, N., Qian, Z., Margala, M. (2015). Aparapi-UCores: A high level programming framework for unconventional cores (pp. 1-6).
  • Margala, M. (2015). Ballistic deflection transistors and their application to THz amplification . Journal of Physics: Conference Series , 647(1).
  • Margala, M. (2015). Optimization of Ballistic Deflection Transistors by Monte Carlo Simulations. Journal of Physics: Conference Series , 647(1).
  • Millithaler, J., I I\~niguez-de-la-Torre, ., Mateos, J., T Gonz\'aIez, ., Margala, M. (2015). Study of surface charges in ballistic deflection transistors. Nanotechnology, 26(48) 485202.
  • Qian, Z., Nasiri, N., Segal, O., Margala, M. (2014). FPGA implementation of low-power split-radix FFT processors (pp. 1-2).
  • Segal, O., Margala, M., Chalamalasetti, S.R., Wright, M. (2014). High level programming framework for FPGAs in the data center (pp. 1-4).
  • Segal, O., Nasiri, N., Margala, M., Vanderbauwhede, W. (2014). High level programming of FPGAs for HPC and data centric applications (pp. 1-3).
  • Qian, Z., Margala, M. (2014). Low power RAM-based hierarchical CAM on FPGA (pp. 1-4).
  • Nasiri, N., Segal, O., Margala, M. (2014). Modified fused multiply-accumulate chained unit (pp. 889-892).
  • Qian, Z., Margala, M. (2014). A novel low-power and in-place split-radix FFT processor (pp. 81-82). Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
  • Vanderbauwhede, W., Frolov, A., Azzopardi, L., Chalamalasetti, S., Margala, M. (2013). High throughput filtering using FPGA-acceleration (pp. 1245-1248). International Conference on Information and Knowledge Management, Proceedings
  • Maltabas, S., Ekekon, O., Kulovic, K., Meixner, A., Margala, M. (2013). An IDDQ BIST approach to characterize phase-locked loop parameters. Proceedings of the IEEE VLSI Test Symposium
  • Iniguez-De-La-Torre, I., Mateos, J., Gonzalez, T., Kaushal, V., Margala, M. (2013). Ballistic deflection transistor: Geometry dependence and boolean operations (pp. 187-190). Proceedings of the 2013 Spanish Conference on Electron Devices, CDE 2013
  • Chalamalasetti, S.b., Lim, K., Wright, M., AuYoung, A., Ranganathan, P., Margala, M. (2013). An FPGA memcached appliance (pp. 245-254). ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
  • Purohit, S.S., Chalamalasetti, S.R., Margala, M., Vanderbauwhede, W.A. (2012). Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
  • Kaushal, V., Iniguez-de-la-Torre, I., Gonzalez, T., Mateos, J., Bongmook Lee, ., Misra, V., Margala, M. (2012). Effects of a High-k Dielectric on the Performance of III"V Ballistic Deflection Transistors. Electron Device Letters, IEEE, 33(8) 1120-1122.
  • Purohit, S., Margala, M. (2012). Investigating the impact of logic and circuit implementation on full adder performance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(7) 1327-1331.
  • Maltabas, S., Kulovic, K., Margala, M. (2012). Novel practical built-in current sensors. Journal of Electronic Testing: Theory and Applications (JETTA), 28(5) 673-683.
  • Purohit, S., Rahul, S., Margala, M., Vanderbauwhede, W. (2012). Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, PP(99) 1-1.
  • Kulovic, K., Margala, M. (2012). Time-based embedded test instrument with concurrent voltage measurement capability. Journal of Electronic Testing: Theory and Applications (JETTA), 28(5) 653-671.
  • Iniguez-De-La-Torre, I., Purohit, S., Kaushal, V., Margala, M., Gong, M., Sobolewski, R., Wolpert, D., Ampadu, P., Gonz�lez, T., Mateos, J. (2011). Exploring digital logic design using ballistic deflection transistors through monte carlo simulations. IEEE Transactions on Nanotechnology, 10(6) 1337-1346.
  • Kaushal, V., Iniguez-De-La-Torre, I., Margala, M. (2011). Nonlinear electron properties of an InGaAs/InAlAs-based ballistic deflection transistor: Room temperature DC experiments and numerical simulations. Solid-State Electronics, 56(1) 120-129.
  • Kaushal, V., Iniguez-De-La-Torre, I., Irie, H., Guarino, G., Donaldson, W.R., Ampadu, P., Sobolewski, R., Margala, M. (2010). A study of geometry effects on the performance of ballistic deflection transistor. IEEE Transactions on Nanotechnology, 9(6) 723-733.
  • Purohit, S., Lanuzza, M., Margala, M. (2010). Design space exploration of split-path data driven dynamic full adder. Journal of Low Power Electronics, 6(4) 469-481.
  • Chalamalasetti, S.R., Purohit, S., Margala, M., Vanderbauwhede, W. (2010). Radiation-hardened reconfigurable array with instruction roll-back. IEEE Embedded Systems Letters, 2(4) 123-126.
  • Diduck, Q., Irie, H., Margala, M. (2009). A room temperature ballistic deflection transistor for high performance applications. International Journal of High Speed Electronics and Systems, 19(1) 23-31.
  • Kaushal, V., Margala, M., Yu, Q., Ampadu, P., Guarino, G., Sobolewski, R. (2009). Current transport modeling and experimental study of THz room temperature ballistic deflection transistors. Journal of Physics: Conference Series, 193.
  • Wieckowski, M., Margala, M., Hu, M.H., Nguyen, H.K. (2009). Differential resistance testing for in p-based semiconductor optical amplifiers. Journal of Lightwave Technology, 27(7) 893-900.
  • Liobe, J., Geisler, R., Margala, M. (2008). A novel application of FM-ADC toward the self-calibration of phase-locked loops. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(9) 2491-2504.
  • Jasionowski, B.J., Lay, M.K., Margala, M. (2007). A processor-in-memory architecture for multimedia compression. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(4) 478-483.
  • Liobe, J., Margala, M. (2007). Novel process and temperature-stable, IDD sensor for the BIST design of embedded digital, analog, and mixed-signal circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(9) 1900-1915.

Selected Presentations

  • Margala, M. and Sule Ozev, Design for Testability for RF Circuits and Systems - IEEE International Test Conference, - Santa Clara, CA
  • - Presentations and seminars given at universities and companies in USA, - - USA: University of Connecticut, University of Massachusetts Amherst, University of Rochester, Nanoelectronic Devices for Defense and Security Conference, Ft. Lauderdale, FL, University of Connecticut, University of Massachusetts Amherst, University of Vermont-Burlington, VT, Analog Devices-Wilmington, MA, University of North Carolina at Charlotte, University of Illinois at Chicago, Boston University, Yale University, SUNY at Buffalo, SUNY at Stony Brook, National Semiconductor, IBM Research-Yorktown Heights, RFMD-Greensboro
  • Exploration of Digital Latch Design using Ballistic Deflection Transistors - Modeling and Simulation - Nanotechnology Materials and Devices Conference , 2015
  • Polaron Effect on Ballistic Transport in Armchair Graphene Nanoribbon - Nanotechnology Materials and Devices Conference , 2015
  • Universal IDDQ BIST for Analog/Mixed-Signal Macros with a Phase-Locked Loop Application - 31st IEEE VLSI Test, 2013 - Berkeley, CA
  • An FPGA Memcached Appliance, FPGA 2013, February 2013. - FPGA 2013, February 2013
  • Design-for-Test Methodologies for Current Tests in Analog/Mixed-Signal Power SOCs - IEEE Midwest Symposium on Circuits and Systems, 2012
  • Evaluating FPGA-acceleration for real-time unstructured search - Proceedings of 2012 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2012
  • A multi-GHz PLL built-in jitter extraction circuit for deep submicron technologies. - 2011 20th European Conference on Circuit Theory and Design, 2011
  • Realization of Logic Operations Through Optimized Ballistic Deflection Transistors - IEEE Compound Semiconductor IC Symposium, 2011
  • A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks - International Conference on High Performance Computing and Simulation (HPCS), 2011 - Istanbul, Turkey
  • General Purpose Logic Gate using Ballistic Nanotransistors - 11th IEEE Conference on Nanotechnology, August 2011 - Portland, OR
  • Performance and Area Efficient Transpose Memory Architecture for High Throughput Adaptive Signal Processing Systems - 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010 - Anaheim, CA.
  • A C++-embedded DSL for programming the MORA soft processor array - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2010 - Rennes, France
  • Data Driven DCVSL: A Clockless Approach to Dynamic Differential Circuit Design - 53rd IEEE Midwest Symposium on Circuits and Systems, 2010 - Seattle, USA.
  • 'Resource-Efficient Implementation of BLUE MIDNIGHT WISH-256 Hash Function on Xilinx FPGA Platform', SHA3. - Resource-Efficient Implementation of BLUE MIDNIGHT WISH-256 Hash Function on Xilinx FPGA Platform',, 2010
  • - 14th International Symposium on Ultrafast Phenomena in Semiconductors, August 2010 - Vilnius, Latvia
  • S. Purohit, I. de laTorre, V. Kaushal, M. Margala, High Performance Digital Circuit Design using Ballistic Nano-electronics, in Proceedings of 53rd IEEE Midwest Symposium on Circuits and Systems 2010 (MWSCAS 2010), August 1-4 2010, Seattle, USA. - 3rd IEEE Midwest Symposium on Circuits and Systems, August 2010 - Seattle, USA.
  • M. El-Hadedy, M. Margala, D. Gligoroski1, S. Johan Knapskog, 'Resource-Efficient Implementation of BLUE MIDNIGHT WISH-256 Hash Function on Xilinx FPGA Platform', Sixth International Conference on Information Assurance and Security (IAS2010), Atlanta , GA, 23-25 August, 2010. - Sixth International Conference on Information Assurance and Security (IAS2010), August 2010 - Atlanta, GA
  • - Photonics Society Summer Conference, July 2010 - Playa del Carmen, Mexico
  • Sub-THz Frequency Analysis in Nano-scale Devices at Room Temperature - 68th Annual Device Research Conference, June 2010 - Indiana USA
  • Room Temperature Nonlinear Ballistic Nanodevices for Logic Applications - 68th Annual Device Research Conference, University of Notre Dame, June 2010 - Indiana USA
  • Low Latency Transpose Memory for High Throughput Signal Processing - 8th IEEE International NEWCAS Conference, June 2010 - Montreal, Quebec, Canada
  • "An Area Efficient Design Methodology for SEU Tolerant Digital Circuits, - 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), May 2010 - Paris, France
  • Low Overhead Soft Error Detection and Correction Scheme for High Performance Pipelined Data paths - 20th ACM Great Lakes Symposium on VLSI, May 2010 - Rhode Island
  • Topology Impact on the Room Temperature Performance of THz-Range Ballistic Deflection Transistors - 20th ACM Great Lakes Symposium on VLSI, May 2010 - Rhode Island
  • A New Built-In IDDQ Testing Method Using Programmable BICS. - IEEE European Test Symposium., May 2010 - Prague, Czech Republic
  • - SPIE Defense, Security and Sensing, April 2010 - Orlando, Florida
  • Ballistic Electronics Ð Breaking the Barrier in Terahertz Speed Processing, in Proceedings of SPIE - Terahertz Physics, Devices, and Systems IV: Advanced Applications in Industry and Defense, April 2010
  • Current transport modeling and experimental study of THz room temperature ballistic deflection transistors - 16th International Conference on Electron Dynamics In Semiconductors, Optoelectronics and Nanostructures (EDISON), August 2009 - Montpellier, France
  • A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model - International Conference on Field Programmable Logic and Applications, August 2009
  • MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor - Fourth NASA/ESA Conference on Adaptive Hardware and Systems, July 2009 - San Francisco, CA.
  • Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor - The International Conference on Engineering of Reconfigurable Systems and Algorithms, July 2009 - Las Vegas, Nevada, USA.
  • A Study of A of Effects Deflector Position Variation on Leakage Current in Ballistic Transistors - IEEE Nanotechnology Materials and Devices Conference, June 2009 - Traverse City, Michigan, USA
  • Study of Leakage Current Mechanisms In Ballistic Deflection Transistors - Great Lakes Symposium on VLSI (GLSVLSI), May 2009 - Boston
  • A 1.2V, 1.02GHz 8 b IEEE/ACMit SIMD Compatible Highly Parallel Arithmetic Data path for Multi-precision Arithmetic - Great Lakes Symposium on VLSI (GLSVLSI), Boston, May 2009 - Boston
  • Varicap Threshold Logic - Great Lakes Symposium on VLSI (GLSVLSI), Boston, May 2009 - Boston
  • "Ballistic deflection transistors and the emerging nanoscale era," - IEEE International Symposium on Circuits and Systems, May 2009 - Taiwan
  • New Performance/Power/Area Efficient Reliable Full Adder Design - IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2009 - Boston
  • Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath - 22nd International Conference on VLSI Design, January 2009
  • Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices - International Conference on Reconfigurable Computing and FPGAs, December 2008
  • - NASA National Nano Engineering Conference., November 2008 - Boston MA
  • PLL BiST - IEEE Defect and Fault Tolerance of VLSI Systems Symposium, October 2008 - Boston, MA
  • Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing, September 2008
  • Power/Throughput/Area Efficient PIM-based Reconfigurable Array for Parallel Processing - IEEE SOC Conference, September 2008 - Newport Beach, CA.
  • A Room Temperature Ballistic Deflection Transistor for High Speed Applications - 2008 Lester Eastman Biennal Conference on High Performance Devices, August 2008
  • A Portless SRAM Cell Using Stunted Wordline Drivers - IEEE International Symposium on Circuits and Systems (ISCAS), May 2008
  • A Room Temperature Ballistic Deflection Transistor for THz Applications - IEEE Advanced Workshop on Frontiers of Electronics (WOFE), Cozumel, Mexico, December 15-19, 2007., December 2007 - Cozumel, Mexico.
  • Nonlinear Transport in the Ballistic T-Branch Junction -- Experiments and Theory - International Symposium on Advanced Nanodevices and Nanotechnology, December 2007 - Waikoloa, Hawai,
  • Novel Process and Temperature-Stable, On-line Solution for Embedded Analog and Mixed-Signal Test - International On-Line Testing Symposium, 2007
  • A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications - Second NASA/ESA Conference on Adaptive Hardware and Systems, (AHS)., 2007
  • Process and Temperature Calibration of PLLs with BiST Capabilities - IEEE International Symposium on Circuits and Systems, May 2007
  • Self-Biased Charge Transfer Sense Amplifier with Integrated Output Latch - International Symposium on Circuits and Systems, May 2007
  • A Low Jitter, Wideband Frequency Synthesizer with Process Tolerant Auto-calibration Technique - IEEE Radio Wireless Symposium (RWS 2007), January 2007
  • Memory-based Circuits and Architectures for Multimedia and Signal Processing SOCs - IEEE International SOC Conference, September 2006 - Austin, TX, September 21, 2006.
  • Adaptable Architectures for Signal Processing Applications - First NASA/ESA Conference on Adaptive Hardware and Systems, (AHS 2006), June 2006
  • A Terahertz Transistor Based on Geometrical Deflection of Ballistic Current - IEEE MTT-S International Microwave Symposium Digest, June 2006
  • New Embedded Core Testing for System-on-Chips and System-in-Packages - IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2006
  • On-Chip Integrated Antennas-The First Challenge for Reliable on-Chip Wireless Interconnects - IEEE Canadian Conference on Electrical and Computer Engineering (CCECE),, May 2006
  • A Versatile Computation Module for Adaptable Multimedia Processors - IEEE International Symposium on Circuits and Systems, May 2006
  • Margala, M., Perri, S., Corsonello, P., Memory-based Circuits and Architectures for Multimedia and Signal Processing SOCs - IEEE International Symposium on Circuits and Systems, May 2006 - Kos, Greece
  • An Integrated Countermeasure against Differential Power Analysis for Secure Smart-Cards - IEEE International Symposium on Circuits and Systems (ISCAS), May 2006
  • Process Tolerant Calibration Circuit for PLL Applications with BIST - IEEE International Symposium on Circuits and Systems (ISCAS), May 2006
  • A 2.4-GHz Auto-calibration Frequency Synthesizer with on-chip Built-In-Self-Test Solution - International Symposium on Circuits and Systems (ISCAS), May 2006
  • A New Test Methodology for DNL Error in Flash ADCs - 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), October 2005
  • A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test - 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFTS), October 2005
  • A new charge-pump based countermeasure against differential power analysis - 6th IEEE International ASIC Conference (ASICON), October 2005 - Shanghai, China
  • A Novel Five-Transistor (5T) SRAM Cell for High Performance Cache - IEEE International SOC Conference (SOCC), September 2005 - Washington, D.C.
  • Cost-Effective Low-Power Processor-In-Memory-based Reconfigurable Datapath for Multimedia Applications - IEEE International Symposium on Low-Power Electronics and Design (ISLPED), August 2005 - San Diego
  • A Design Approach for a 6.7-mW 5-GHz CMOS Frequency Synthesizer using Dynamic Prescaler - IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2005 - Cincinnati, Ohio
  • Non-Intrusive Testing Methodology for CMOS RF LNAs - IEEE RF Integrated Circuits Symposium, June 2005 - Long Beach, CA
  • A New SOC Test Architecture with RF/Wireless Connectivity - IEEE European Test Symposium (ETS), May 2005 - Tallin Estonia
  • A 32KB SRAM Cache Using Current Mode Operation and Asynchronous Wave-Pipelined Decoders - IEEE International System-on-Chip Conference (SOCC), September 2004
  • A. Gopalan, P.R.Mukund, M. Margala, A Non-Intrusive Self-Test Methodology for RF CMOS Low Noise Amplifiers - IEEE International Mixed-Signal Test Workshop, June 2004 - Portland, Oregon
  • Deep-submicron CMOS Design of High-performance Low-Power Flash/Folding Analog-to-Digital Converters - Canadian Conference on Electrical and Computer Engineering, May 2004
  • Low-Power and High-Speed Digital Correlator for Radio Astronomy - IEEE Canadian Conference on Electrical and Computer Engineering, May 2004
  • Nanotechnology based Energy Generation from Thermal Radiation - IEEE Canadian Conference on Electrical and Computer Engineering, May 2004
  • 6-BIT Low Power Low Area Frequency Modulation Based Flash ADC - IEEE International Symposium on Circuits and Systems (ISCAS), May 2004
  • A 5.1-GHz CMOS PLL based Integer-N Frequency Synthesizer with Ripple-free Control Voltage and Improved Acquisition Time - IEEE International Symposium on Circuits and Systems (ISCAS), May 2004
  • SOBEL Edge Detection Processor for a Real-Time Volume Rendering System - IEEE International Symposium on Circuits and Systems (ISCAS), May 2004
  • Design of Wireless Sub-Micron Characterization System - 22nd IEEE VLSI Test Symposium (VTS), April 2004
  • Fault Diagnosis of a GHz CMOS LNA Using High-speed ADC-based BIST - IEEE Defect-Based Testing Workshop, April 2004 - Napa, CA
  • Cost Model Analysis of DFT based Fault Tolerant SOC Designs - 5th IEEE International Symposium on Quality Electronic Design (ISQED), March 2004
  • A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems - 7th IEEE International Conference VLSI Design, January 2004 - India
  • 1-V ADPCM Processor for Low-Power Wireless Applications - 12th IFIP International Conference on VLSI-SOC, December 2003 - Darmstadt, Germany
  • 1.8V 0.18_m CMOS Novel successive Approximation ADC, in Proceedings of 12th IFIP International Conference on VLSI-SOC, Darmstadt, pp.375-379, Germany, 1-4 December, 2003. - 12th IFIP International Conference on VLSI-SOC, December 2003 - Darmstadt, Germany
  • High-Performance Low-Power Analog-to-Digital Converter Design in Deep-submicron CMOS - 12th IFIP International Conference on VLSI-SOC, December 2003 - Darmstadt, Germany
  • Control Constrained Resource Partitioning for Complex SoCs - IEEE Defect and Fault-Tolerance of VLSI Systems Symposium, November 2003 - Cambridge, MA
  • Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits - IEEE Defect and Fault-Tolerance of VLSI Systems Symposium., November 2003 - Cambridge, Massachusetts
  • A Low Power 6-b Integrating-Pipeline Hybrid Analog-to-Digital Converter - 16th Annual IEEE International SOC Conference, September 2003 - Portland, Oregon
  • A New Distributed Test Control Architecture with Multihop Wireless Test Connectivity and Communication for Gigahertz System-on-Chips - IEEE North Atlantic Test Workshop, May 2003 - Montauk, NY
  • CMBIST-A Current Monitor based Built-In-Self-Test for Mixed Embedded Environments - International Workshop on Defect-Based Testing, April 2003 - Napa, California
  • Neural Networks-Based Parametric Testing of Analog ICs - IEEE International Symposium on Defect and Fault-Tolerance of VLSI Systems., October 2002 - Vancouver, BC, Canada
  • Highly Efficient Digital CMOS Accelerator for Image and Graphics Processing - 15th Annual IEEE International ASIC/SOC Conference, September 2002 - Rochester, NY
  • Application-Specific Low-Voltage Current Amplifier for System-on-Chip Iddq Test - 9th IEEE International Conference on Electronics, Circuits, and Systems (ICECS),, September 2002 - Dubrovnik, Croatia
  • A Novel Self-Repairable Parallel Multiplier Architecture, Design and Test - 3rd IEEE Asia-Pacific Conference on ASICs, August 2002 - Taipei, Taiwan
  • Low-Voltage Power-Efficient Adder Design - 45th IEEE Midwest Symposium on Circuits and Systems, August 2002 - Tulsa, Oklahoma
  • Low-Voltage Analog Current Detector Supporting At-Speed BIST - IEEE International Symposium on Circuits and Systems (ISCAS 2002), May 2002 - Phoenix, Arizona, USA
  • Scalable Current Sensor for Sensitive Fault Detection in Very Deep Sub-micron CMOS - IEEE North Atlantic Test Workshop, Montauk, NY., May 2002 - Montauk, NY
  • Minimizing Concurrent Test Time in SoC's by Balancing Resource Usage - ACM Great Lakes Symposium on VLSI, New York City, NY., April 2002 - New York City, NY
  • Novel Design and Verification of a 16 x 16-b Self-Repairable Reconfigurable Inner Product Processor - ACM Great Lakes Symposium on VLSI, New York City, NY., April 2002 - New York City, NY
  • A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test - IEEE Computer Society Symposium on VLSI, Pittsburg, PA., April 2002 - Pittsburg, PA
  • An Embedded Iddq/_Iddq BIST Architecture for Analog and Mixed-Signal Cores in System-on-Chip Applications - 11th IFIP International Conference on VLSI-SOC, December 2001 - Montpelier, France.
  • New Approach to Design for Reusability of Datapath Architectures - 11th IFIP International Conference on VLSI-SOC., December 2001 - Montpelier, France.
  • A Low Power DSP for an Embedded MP3 Decoder Core - 27th Annual Conference of the IEEE Industrial Electronics Society, December 2001 - Denver, Colorado, USA.
  • Low-Voltage 0.25_m CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors - 11th IFIP International Conference on VLSI-SOC, 2001
  • Design Verification and DFT for an Embedded Reconfigurable Low-Power Multiplier in System-on-Chip Applications - 14th IEEE International ASIC/SOC Conference, Arlington, September 2001 - Arlington, VA
  • A Novel Wide-Band CMOS Current Amplifying Cell and Its Application in Power Supply Current Monitoring - 8th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Malta,, September 2001 - Malta
  • Low-Power Canonical Signed Digit (CSD) Double Pass-Transistor Logic Based Multiplier for Digital FIR Filters - IEEE Electronics, Circuits and Systems Conference., September 2001 - Slovakia
  • Power-Efficiency Driven Device Sizing of Pass-Transistor Digital Circuits in Low-Voltage CMOS - IEEE International Workshop on Power, Modeling, Optimization and Simulation (PATMOS2001), September 2001 - Switzerland
  • Fast and Low-Power Inner Product Processor - IEEE International Symposium on Circuits and Systems (ISCASÕ2001), May 2001 - Sydney, Australia,
  • Using Computational RAM for Volume Rendering - 13th Annual IEEE International ASIC/SOC Conference., September 2000 - Washington, DC.
  • Dragic, S., Margala, M., El-Abasiry, A., Ekpe S. and Stopjakova, V., 1-V Fast Iddq Current Sensor for On-Line Mixed-Signal/Analog Test. - IEEE International On-Line Test Workshop (IOLTWÕ2000), July 2000
  • Wireless Testing Techniques and Circuits for Deep-Submicron VLSI Circuits - Wireless 2000 Conference,, July 2000
  • A Fault-Injection Technique for Improved Reliability and Fault-Tolerance of Analog Circuits - IEEE International Mixed-Signal Test Workshop (IMSTWÕ2000), June 2000
  • Pecuh, I., Margala, M. and Stopjakova, V., An On-Chip Current Monitor for Low-Voltage Mixed-Signal Test, - IEEE International Mixed-Signal Test Workshop (IMSTWÕ2000), June 2000
  • Investigation into the use of Processors for Volume Rendering - International Symposium on Computer Architecture (ISCA), June 2000
  • A VHDL Implementation of a Shearing Unit for Shear-Warp Factorization Volume Rendering - IEEE Canadian Conference on Electrical and Computer Engineering (CCECEÕ2000), May 2000 - Halifax, Nova Scotia, Canada.
  • Addition and Multiplication Schemes for Energy-Efficient DSP - IEEE Canadian Conference on Electrical and Computer Engineering (CCECEÕ2000), May 2000 - Halifax, Nova Scotia, Canada
  • Analysis of Temperature Effects on Maximum Power-Efficiency of Pass-Transistor Logic Networks in Low-Voltage CMOS - IEEE Canadian Conference on Electrical and Computer Engineering (CCECEÕ2000), May 2000 - Halifax, Nova Scotia, Canada
  • Low-Power Wireless Communication Systems - IEEE Canadian Conference on Electrical and Computer Engineering (CCECEÕ2000), May 2000 - Halifax, Nova Scotia, Canada.
  • A Fast Iddx Monitoring Scheme for Testing Battery-Operated VLSI Circuits - IEEE European Test Workshop (ETWÕ2000), May 2000
  • "Optimization Techniques for Maximum Power-Efficiency of Deep-Submicron CMOS Digital CircuitsÓ. - IEEE International Symposium on Circuits and Systems (ISCASÕ2000), May 2000
  • Testing of Deep-Submicron Battery-Operated Circuits using New Fast Current Monitoring Scheme - IEEE International Workshop on Defect Based Testing, April 2000
  • Fast Current Monitoring Technique for Low-Voltage VLSI Testing - IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECSÕ2000), April 2000
  • "1.5V Iddq/Iddt Current Monitor". - 1999 IEEE Canadian Conference on Electrical and Computer Engineering, 1999 - Alberta, Canada
  • "High-Performance Low-Power Inner-Product Processor". - 1999 IEEE Canadian Conference on Electrical and Computer Engineering., 1999 - Edmonton, Alberta, Canada
  • "0.35_m CMOS 1.5-V Current Sensor. - 1999 IEEE European Test Workshop, 1999
  • "Low-Power SRAM Circuit Design" - 1999 IEEE International Workshop on Memory Technology, Design and Testing., 1999
  • "Low-Voltage Low-Power Current Monitor for On-Line Testing". - 5th IEEE International Mixed-Signal Testing Workshop, 1999 - British Columbia, Canada.
  • "Low-Power Low-Voltage 4-2 Compressors for VLSI Applications" - IEEE Alessandro Volta Memorial Workshop on Low Power Design, 1999
  • " Digital Controller for an Opto-Electronic Switch(OES) with DSP Capabilities". - IEEE Canadian Conference on Electrical and Computer Engineering, 1999 - Edmonton, Alberta, Canada
  • "High-Speed Image Composition with Enhanced Multiplier Structure", - IEEE Canadian Conference on Electrical and Computer Engineering, 1999 - Edmonton, Alberta, Canada
  • Margala, M., Low-Power SRAMs for Battery Operation, 1999 IEEE International Workshop on Memory Technology, Design and Testing, in Proceedings, p.6, 1999. - IEEE International Workshop on Memory Technology, Design and Testing, 1999
  • ."A Simplified Energy Projection and Applications of Transfer Function in Isometric Volume Rendering" - 1999 IEEE Canadian Conference on Electrical and Computer Engineering, May 1999
  • "Low-Voltage Power-Efficient BiDPL Logic Design and Applications" - IEEE Canadian Conference on Electrical and Computer Engineering, 1998
  • Margala, M. and Durdle, N.G., "200MHz 0.8um CMOS Gradient Vector Processor for Real-Time Execution" - IEEE Canadian Conference on Electrical and Computer Engineering, 1998
  • Rodnunsky, N.L., Margala, M. and Durdle, N.G., "Power Estimation of CMOS Circuits via power Software". - IEEE Canadian Conference on Electrical and Computer Engineering, 1998
  • "A Gradient Processor for High Speed Medical Imaging". - 7th Annual IEEE International ASIC Conference and Exhibit, 1994
  • "A 33MHz 16-bit Gradient Calculator for Real-Time Volume Imaging" - 9th Eurographics Workshop on Computer Graphics Hardware, 1994

Selected Intellectual Property

  • Patent - Diduck, Q., Margala, M."Ballistic Deflection Transistor and Logic Circuits," US Patent 7,576,353 United States
  • Patent - Diduck, Q., Margala, M."Frequency Modulation Based ADC," US Patent 7,425,915 United States
  • Patent - Lin, R., Margala, M."Multiplier-Based Processor-in-Memory Architectures for Image and Graphics Processing," US patent 7,167,890 B2. United States

Selected Contracts, Fellowships, Grants and Sponsored Research

  • Collaborative Research: Ballistic Deflection Transistors for THz Amplification (2012), Contract -
    Margala, M. (Principal)
  • US -Turkey Collaborative Effort in Advancing Assistive Technology based Education (2010), Grant -
    Margala, M. (Principal)
  • DFX Solutions for PLLs on Advanced Digital Processes (2009), -
    Margala, M. (Principal)
  • Demonstration of FPGA Acceleration for Information-Centric Workloads (2011), -
    Margala, M. (Principal)
  • ARRA - MRI: Acquisition of the Multi-Probe Wide-Temperature Parameter Analysis Sy (2009), Grant -
    Margala, M. (Principal)
  • NIRT: Utilization of Ballistic Deflection Phenomena for Room Temperature Device a (2007), Grant - NATIONAL SCIENCE FOUNDATION
    Margala, M. (Principal)
  • Multi-Probe Wide-Temperature Parameter Analysis System for Low-Voltage Low-Noise (2009), Grant -
    Margala, M. (Principal)
  • Room Temperature Ballistic Deflection Transistor and Circuits (2007), Grant -
    Margala, M. (Principal)
  • MRI: Acquisition of the Multi-Probe Wide-Temperature Parameter Analysis System for Low-Voltage Low-Noise Measurements (2009), - National Science Foundation
    Armiento, C. (Co-Principal), Margala, M. (Principal)
  • Modeling of GaN Structures for Reliability (2008), Contract -
    Margala, M. (Principal)

Quick Links