Conference & Workshop Papers

C35 Chen Xu, Xiaoban Wu, Yan Luo, Brian Tierney and Jeronimo Bezerra, Pepple: Programmable Network Measurement for Troubleshooting Soft Failures, IEEE 37th Sarnoff Symposium, Newark NJ, Sept 19-21, 2016.

C34  Peilong Li, Yan Luo, P4GPU: Acceleration of Programmable Data Plane Using a CPU-GPU Heterogeneous Architecture, IEEE 17th International Conference on High Performance Switching and Routing, Yokohama, Japan, June 14-17, 2016.

C33  Lu He, Tim Miskell, Rui Liu, Hengyong Yu, Huijuan Xu, Yan Luo, Scalable 2K K-SVD Parallel Algorithm for Dictionary Learning on GPU, ACM International Conference on Computing Frontiers 2016, May 16 – 18, 2016, Como, Italy.

C32 2015 Lu He, Yan Luo, Rui Liu, Hengyong Yu, Yu Cao, Xuzhou Chen, Seung Woo Son, Bisection and Twisted SVD on GPU, IEEE High Performance Extreme Computing Conference, Waltham, MA, Sept 15-17, 2015.

C31 2015 Peilong Li, Yan Luo, Ning Zhang and Yu Cao, HeteroSpark: A Heterogeneous CPU/GPU Spark Platform for Machine Learning Algorithms, IEEE Conference on Networking, Architecture and Storage, Boston, MA, Aug 6-8, 2015.

C30 2014 Peilong Li, Xiaobing Huang, Tian Zhao, Yan Luo and Yu Cao, Sparkling: Identification of Task Skew and Speculative Partition of Data for Spark Applications, Spark Summit, July 2014.

C29 2014 Lu He, Yan Luo and Yu Cao, “Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition”, In Proceedings of The 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 11-13, Boston, MA, 2014.

C28 2012 Sen Su, Zhongbao Zhang, Xiang Cheng, Yiwen Wang, Yan Luo and Jie Wang, Energy-aware Virtual Network Embedding Through Consolidation, The 1st IEEE INFOCOM Workshop on Communications and Control for Sustainable Energy Systems: Green Networking and Smart Grids, March 25- 30, 2012, Orlando FL.

C27 2012 Peilong Li, Yan Luo, Thomas Calloway, Imran Vakil, Exploration of Memory Hierarchy for Heterogeneous Computing Architecture, The 3rd Workshop on SoCs, Heterogeneous Architectures and Workloads, Feb 26, 2012, New Orleans, LA.

C26 2012 Xuzhou Chen, Yan Luo and Jie Wang, Virtual Network Embedding with Border Matching, The 4th IEEE International Conference on Communication Systems and Networks, Jan 3-7, 2012, Bangalore, India.

C25 2011 Xin Sun, Sen Su, Lei Jiang, Shuang Chi and Yan Luo, Multi-dimensional Resource Integrated Scheduling in a Shared Data Center, The First International Workshop on Data Center Performance, Minneapolis, MN, June 5, 2011.

C24 2011 Jonathan Labroad, Yan Luo, Sairhual Chalamalasetti, Timothy Ficarra, and Martin Margala, Reconfigurable Logic Accelerated Heterogeneous Multicore Architecture for Dynamic Workloads, 2nd Workshop on SoC Architecture, Accelerators and Workloads, in conjunction with IEEE HPCA’11, San Antonio, TX, Feb 12, 2011.

C23 2010 Yan Luo, Eric Murray, Timothy Ficarra, Accelerated Virtual Switching with Programmable NICs for Scalable Data Center Networking, ACM SIGCOMM Virtualized Infrastructure Systems and Architectures (VISA) Workshop, New Delhi, India, Sept 3, 2010.

C22 2010 Sanping Li, Yan Luo, High Performance Flow Feature Extraction with Multicore Processors, IEEE International Conference on Network, Architecture and Storage, Macau, China, July 15-17, 2010 (Best Paper Award).

C21 2009 Yan Luo, Pablo Cascon, Eric Murray, Julio Ortega, Accelerating OpenFlow Switching with Network Processors, ACM Symposium on Architectures for Networking and Communications Systems, Princeton, NJ, Oct 19, 2009.

C20 2009 Yan Luo, Sanping Li, Yu Liu, A DFA-Based Regular Expression Matching Engine on a NetFPGA Platform, NetFPGA Developers Workshop, Stanford University, Palo Alto, CA, Aug 12-24, 2009.

C19 2009 Sanping Li and Yan Luo, Discernibility Analysis and Accuracy Improvement of Machine Learning Algorithms for Network Intrusion Detection, IEEE International Conference on Communications, Dresden, Germany, June 14-18, 2009.

C18 2009 Yan Luo, Ke Xiang, Jie Fan and Chunhui Zhang, Distributed Intrusion Detection with Intelligent Network Interfaces for Future Networks, IEEE International Conference on Communications, Dresden, Germany, June 14- 18, 2009.

C17 2009 Yan Luo, Chunhui Zhang, A Performance Study of Network I/O Accelerators for Network Virtualization, Workshop on The Influence of I/O on Microprocessor Architecture (IOM-2009) co-located with HPCA15, Raleigh, NC, February 15, 2009.

C16 2008 Yan Luo, Ke Xiang and Sanping Li, Acceleration of Decision Tree Searching for IP Traffic Classification, ACM Symposium on Architectures for Networking and Communications Systems, San Jose, CA, Nov 6-7, 2008.

C15 2008 Yan Luo and Chunhui Zhang, The Design of A Programmable Network Edge Node with Hybrid Multi-core Processors for Virtual Networks, IEEE International Conference on Computer Communications and Networks, St. Thomas, VI, August 3-7, 2008.

C14 2008 Piti Piyachon and Yan Luo, Design of High Performance Pattern Matching Engine Through Compact Deterministic Finite Automata, IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, June 8-13, 2008.

C13 2008 Yan Luo and Jie Fan, Fault Tolerant Practices on Network Processors for Dependable Network Processing, 13th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems, in conjunction with IPDPS'08, Miami, FL, April 14-18, 2008.

C12 2008 Song Huang, Yan Luo and Wu-chun Feng, Modeling and Analysis of Power in Multicore Network Processors, Fourth IEEE Workshop on High-Performance, Power-Aware Computing, in conjunction with IPDPS'08, Miami, FL, April 14-18, 2008.

C11 2007 Chris Hayes and Yan Luo, DPICO: A High Speed Deep Packet Inspection Engine using Compact Finite Automata, ACM Symposium on Architectures for Networking and Communications Systems, Orlando, FL, Dec 3-4, 2007.

C10 2007 Piti Piyachon, Yan Luo, Compact State Machines for High Performance Pattern Matching, IEEE/ACM Design Automation Conference (DAC), San Diego, CA, June 4-8, 2007.

C9 2006 Piti Piyachon, Yan Luo, Efficient Memory Utilization on Network Processors for Deep Packet Inspection, ACM Symposium on Architecture for Networking and Communications Systems, San Jose, CA, Dec 3-5, 2006.

C8 2005 Li Zhao, Yan Luo, Laxmi Bhuyan, Ravi Iyer, SpliceNP: A TCP Splicer using Network Processors, ACM Symposium on Architecture for Networking and Communications Systems, Princeton, NJ, Oct 27-28, 2005.

C7 2005 Jingnan Yao, Yan Luo, Laxmi Bhuyan, Ravi Iyer, Optimal Network Processor Topologies for Efficient Packet Processing, IEEE Globecom 2005, St Louis, MO, Nov 28-Dec 2, 2005.

C6 2005 Li Zhao, Yan Luo, Laxmi Bhuyan, Ravi Iyer, Implementation and Design of A Content-aware Switch Using A Network Processor, IEEE Symposium on High Performance Interconnects, Palo Alto, CA, August 17-19, 2005.

C5 2005 Yan Luo, Jia Yu, Jun Yang, Laxmi Bhuyan, Low Power Network Processor Design Using Clock Gating, IEEE/ACM Design Automation Conference (DAC), Ahaheim, California, June 13-17, 2005.

C4 2004 Xi Chen, Yan Luo, Harry Hsieh, Laxmi Bhuyan, Felice Balarin, Utilizing Formal Assertions for System Design of Network Processors, Design Forum, Design Automation and Test in Europe (DATE), 2004.

C3 2002 Yan Luo, Li Zhao, Laxmi Bhuyan, Walid Najjar, Evaluating the Impact of Architectural Features on Communication Benchmarks, Communications in Computing, Nevada, USA, June 24-27, 2002.

C2 2001 David Watson, Yan Luo, and Brett Fleisch, Experiences with Oasis+: A Fault Tolerant Storage System, Proceedings of the IEEE International Conference on Cluster Computing, Newport Beach, CA, Oct 8-11 2001.

C1 2000 David Watson, Yan Luo, and Brett Fleisch, The Oasis+ Dependable Distributed Storage System, Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing, Los Angeles, CA, December 18-19, 2000.